/**********************************************************************************************************************
* COPYRIGHT 
* ------------------------------------------------------------------------------------------------------------------- 
* Copyright (c) iSOFT INFRASTRUCTURE SOFTWARE CO., LTD. This software is proprietary to 
* iSOFT INFRASTRUCTURE SOFTWARE CO., LTD., and all rights are reserved by iSOFT INFRASTRUCTURE SOFTWARE CO., LTD. 
* Without the express written permission of the company, no organization or individual may copy, install, trial, 
* distribute, or reverse engineer this software. For terms of use and further details, please refer to the End User 
* License Agreement (EULA) or contact us business@i-soft.com.cn for more assistance. 
* 
* This file contains code from EasyXMen, which is licensed under the LGPL-2.1. However, due to a special exception, 
* you are not required to comply with the provisions of section 6a of LGPL-2.1. Specifically, you may distribute 
* your software, including this file, under terms of your choice, including proprietary licenses, without needing to 
* provide the source code or object code as specified in section 6a. For more details, please refer to the project's 
* LICENSE and EXCEPTION files and the specific exception statement.  
* ------------------------------------------------------------------------------------------------------------------- 
* FILE DESCRIPTION 
* ------------------------------------------------------------------------------------------------------------------- 
*  @MCU                : S32K148 
*  @file               : Os_Intvet.c 
*  @license            : Evaliation 
*  @licenseExpiryDate  : 2025-02-09 23:10:53 
*  @date               : 2025-01-18 17:09:19 
*  @customer           : EasyXMen User 
*  @toolVersion        : 2.0.18 
*********************************************************************************************************************/ 

/*=======[I N C L U D E S]====================================================*/
#include "Os_Cfg.h"
#include "Os_Internal.h"
#include "Arch_Processor.h"

/*=======[V E R S I O N   I N F O R M A T I O N]===============================*/
#define     OS_VECTOR_C_AR_MAJOR_VERSION              19U
#define     OS_VECTOR_C_AR_MINOR_VERSION              11U
#define     OS_VECTOR_C_AR_PATCH_VERSION              0U
#define     OS_VECTOR_C_SW_MAJOR_VERSION              2U
#define     OS_VECTOR_C_SW_MINOR_VERSION              0U
#define     OS_VECTOR_C_SW_PATCH_VERSION              0U

/*=======[V E R S I O N  C H E C K]===========================================*/
#if (OS_VECTOR_C_AR_MAJOR_VERSION != OS_CFG_H_AR_MAJOR_VERSION)
    #error "Os_Intvet.c:Mismatch in Specification Major Version"
#endif
#if (OS_VECTOR_C_AR_MINOR_VERSION != OS_CFG_H_AR_MINOR_VERSION)
    #error "Os_Intvet.c:Mismatch in Specification Minor Version"
#endif
#if (OS_VECTOR_C_AR_PATCH_VERSION != OS_CFG_H_AR_PATCH_VERSION)
    #error "Os_Intvet.c:Mismatch in Specification Patch Version"
#endif
#if (OS_VECTOR_C_SW_MAJOR_VERSION != OS_CFG_H_SW_MAJOR_VERSION)
    #error "Os_Intvet.c:Mismatch in Specification Major Version"
#endif
#if (OS_VECTOR_C_SW_MINOR_VERSION != OS_CFG_H_SW_MINOR_VERSION)
    #error "Os_Intvet.c:Mismatch in Specification Minor Version"
#endif

/*=======[M A C R O S]========================================================*/
#define     OS_ARCH_INT_CORE0                  OS_ARCH_INT_CPU0

/*==========[I S R]===========================================================*/
/* PRQA S 1505,3408,1840,3335,2981,3432,0306,3415,0303,3469++ */ /* MISRA Rule 8.7,8.4,10.4,17.3,2.2,20.7,11.4,13.5,11.4 */
/* --------------------CORE0-------------------- */
#define OS_START_SEC_CODE_FAST
#include "Os_MemMap.h"
FUNC(void, OS_CODE_FAST) Os_ISR_SYSTEM_TIMER_CORE0(void)
{
    OS_ARCH_ISR2_PROLOGUE(Os_GetObjLocalId(CFG_SYS_TIMER_CORE0_ID));
    Os_ArchSystemTimerCore0();
    OS_ARCH_ISR2_EPILOGUE();
}
#define OS_STOP_SEC_CODE_FAST
#include "Os_MemMap.h"
#define OS_START_SEC_CODE_FAST
#include "Os_MemMap.h"
FUNC(void, OS_CODE_FAST) Os_ISR_CAN0_ORed(void)
{
    OS_ARCH_ISR2_PROLOGUE(Os_GetObjLocalId(CFG_ISR_CAN0_ORed_ID));
    CAN0_ORed();
    OS_ARCH_ISR2_EPILOGUE();
}
#define OS_STOP_SEC_CODE_FAST
#include "Os_MemMap.h"
#define OS_START_SEC_CODE_FAST
#include "Os_MemMap.h"
FUNC(void, OS_CODE_FAST) Os_ISR_CAN0_ORed_0_15_MB(void)
{
    OS_ARCH_ISR2_PROLOGUE(Os_GetObjLocalId(CFG_ISR_CAN0_ORed_0_15_MB_ID));
    CAN0_ORed_0_15_MB();
    OS_ARCH_ISR2_EPILOGUE();
}
#define OS_STOP_SEC_CODE_FAST
#include "Os_MemMap.h"
#define OS_START_SEC_CODE_FAST
#include "Os_MemMap.h"
FUNC(void, OS_CODE_FAST) Os_ISR_CAN0_ORed_16_31_MB(void)
{
    OS_ARCH_ISR2_PROLOGUE(Os_GetObjLocalId(CFG_ISR_CAN0_ORed_16_31_MB_ID));
    CAN0_ORed_16_31_MB();
    OS_ARCH_ISR2_EPILOGUE();
}
#define OS_STOP_SEC_CODE_FAST
#include "Os_MemMap.h"
#define OS_START_SEC_CODE_FAST
#include "Os_MemMap.h"
FUNC(void, OS_CODE_FAST) Os_ISR_FTM0_Ch0_Ch1(void)
{
    OS_ARCH_ISR2_PROLOGUE(Os_GetObjLocalId(CFG_ISR_FTM0_Ch0_Ch1_ID));
    FTM0_Ch0_Ch1();
    OS_ARCH_ISR2_EPILOGUE();
}
#define OS_STOP_SEC_CODE_FAST
#include "Os_MemMap.h"
/* PRQA S 1505,3408,1840,3335,2981,3432,0306,3514,0303-- */ /* MISRA Rule 8.7,8.4,10.4,17.3,2.2,20.7,11.4,13.5,11.4 */

/* ------------------Interrupt install-------------------- */
/* PRQA S 1532,2016,0303,3432++ */ /* MISRA Rule 8.7,16.4,11.4,20.7 */
#define OS_START_SEC_CODE_FAST
#include "Os_MemMap.h"
FUNC(void, OS_CODE) Os_IntHandler(void)
{
    /* Just ignore this interrupt.  */
    while(1){}
}
#define OS_STOP_SEC_CODE_FAST
#include "Os_MemMap.h"

#define OS_START_SEC_CODE_FAST
#include "Os_MemMap.h"
FUNC(void, OS_CODE) Os_ArchInitIntPrio(void)
{
    Os_CoreIdType coreID = Os_SCB.sysCore;
    switch(coreID)
    {
        case 0:
                Os_InterruptInstall(OS_SRC_SYSTEM_TIMER_CORE0_ADDR, 10U, OS_ARCH_INT_CORE0, Os_ISR_SYSTEM_TIMER_CORE0);
                Os_InterruptInstall(OS_SRC_CAN0_ORed_ADDR, 1U, OS_ARCH_INT_CORE0, Os_ISR_CAN0_ORed);
                Os_InterruptInstall(OS_SRC_CAN0_ORed_0_15_MB_ADDR, 1U, OS_ARCH_INT_CORE0, Os_ISR_CAN0_ORed_0_15_MB);
                Os_InterruptInstall(OS_SRC_CAN0_ORed_16_31_MB_ADDR, 1U, OS_ARCH_INT_CORE0, Os_ISR_CAN0_ORed_16_31_MB);
                Os_InterruptInstall(OS_SRC_FTM0_Ch0_Ch1_ADDR, 1U, OS_ARCH_INT_CORE0, Os_ISR_FTM0_Ch0_Ch1);
        break;
        default:
        Os_Panic();
        break;
    }
    return;
}
#define OS_STOP_SEC_CODE_FAST
#include "Os_MemMap.h"
/* PRQA S 1532,2016,0303,3432,3469-- */ /* MISRA Rule 8.7,16.4,11.4,20.7 */
/*=======[E N D   O F   F I L E]==============================================*/

